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data sheet june 1999 CDRM622 622 mbits/s multichannel digital timing recovery features n receives scrambled serial data at sts-12/stm-4 (622.08 mbits/s) rate. n demultiplexes serial data to 77.76 mbytes/s paral- lel byte wide data with aligned 77.76 mhz clock. n synthesizes 622.06 mhz clock with on-chip pll, requiring only 77.76 mhz input reference clock and one external resistor. n multiplexes parallel 77.76 mbytes/s data to 622 mbits/s serial data for transmission. n incorporates n = 1 to 16 channels with modular design. implemented in lucent technologies microelectronics group hl250c technology. n meets type b jitter tolerance specification of itu-t recommendation g.958. n sources stable clock in absence of data transitions once the clock synthesizer has acquired lock. n uses single, low-voltage (3.3 v 5%) supply. n includes built-in test circuitry such as high-speed loopback of transmit data into receiver. n iddq compatible. n powers down the receiver on per-channel basis. n allows jtag access to high-speed data paths. description the CDRM622 provides a physical medium for high- speed asynchronous serial data transfer between asic devices. devices can be on the same pc- board, or on separate boards connected across a backplane, or connected by cables. the macrocell is intended for, but not limited to, terminal equipment in sonet/sdh and atm systems. the macrocell consists of three functional blocks. the receiver accepts 622.08 mbits/s serial data. based on data transitions, the receiver selects an appropriate 622 mhz clock phase for each channel to retime the data, then demultiplexes down to 77.76 mbytes/s parallel bytes and a 77.76 mhz clock. the transmitter operates in the reverse direction. 77.76 mbytes/s parallel bytes are multiplexed up to 662.08 mbits/s serial data for off-chip communica- tion. the clock synthesizer generates the necessary 622.08 mhz clock for operation from a 77.76 mhz reference. figure 1 illustrates the function of the mac- rocell. the hard macrocell can be supplied for up to 16 data channels. multiple macrocells can be used on a sin- gle device. the macrocell is intended to be used with high-speed differential i/o buffers for the 622 mbits/s serial data streams and the 77.76 mhz reference clock. common selections are low-voltage differential swing (lvds) or pecl. the i/o buffers are part of our standard-cell asic library and are not included in the macrocell to allow for flexibility.
CDRM622 data sheet 622 mbits/s multichannel digital timing recovery macrocell june 1999 2 lucent technologies inc. description (continued) 5-5833 (f).br.2 figure 1. CDRM622 block diagram tstmode tstshftld built-in rx cdr serial to parrallel (622 mbits/s to 78 mbytes/s) demux select 622.08 mhz test clock/data alignment synthesizer pll parrallel to serial (78 mbytes/s to 622 mbits/s) mux boundary scan loopbkch[(n C 1):0] ld[(n C 1):0]r[7:0] mreset (master reset) ecsel exdnup etoggle tstphase tstclk bypass loopbken hdin[(n C 1):0] 622 mbits/s data rext pllpwrdn ref78 77.76 mhz hdout[(n C1):0] 622 mbits/s data bscanen resettn (test) tstmux[8:0] bsipad[(n C 1):0] lckr[(n C 1):0] resetrn tstclk bypass (test) rxpwrdn[(n C 1):0] lck78 77.76 mhz 77.76 mbytes/s ldat[(n C 1):0] x[7:0] bsopad[(n C 1):0] (boundary scan) 1 2 n tx 1 2 n (boundary scan) 77.76 mhz 77.76 mbytes/s retime
data sheet CDRM622 june 1999 622 mbits/s multichannel digital timing recovery macrocell 3 lucent technologies inc. description (continued) physical size the macrocell is able to support up to 16 channels of serial data; however, the physical design will be limited to two sizes (8 and 16). unused receivers will be powered down for specific applications as the physical size of the mac- rocell does not vary directly with channels. the physical dimensions of a 16-channel macrocell are approximately square at 2.2 mm per side. power dissipation at 3.3 v, power is estimated by 300 mw + 50 mw per rx channel + 10 mw per tx channel. device io buffers device io buffers are not part of the hard macrocell. this allows customers to choose the most appropriate inter- face levels without disturbing the macrocell. common choices of device interface levels are lvds (low-voltage dif- ferential swing) and pecl. device pinout is also flexible. appropriate buffering will be added to the device by lucent technologies microelectronics group to ensure data integrity between the io buffers and the macrocell.
CDRM622 data sheet 622 mbits/s multichannel digital timing recovery macrocell june 1999 4 lucent technologies inc. hardware interface low-speed 77.76 mbytes/s interface the internal timing performance of the macrocell is independent of the remaining device logic with the exception of the low-speed interface. the macrocell sources clock and data bytes for each channel to be captured and pro- cessed by the device logic. in the other direction, the device logic sources data bytes to be captured and processed by the macrocell. these interfaces are generally designed and verified using static timing analysis. figure 2 illus- trates these interfaces and their associated timing. input capacitance for all digital inputs, the input capacitance at the boundary of the macrocell is 0.02 pf. output signal drive strength for all low-speed outputs, the output driver strength is equivalent to that of a lucent-type sbns standard cell. (see hl250c 3.3 volt 0.25 m cmos standard-cell librar y , s y stem asic data book march 1998 ( mn97-066asic )) . table 1. functional si g nals signal name type description hdin[(n C 1):0] i 622.08 mbits/s serial data inputs. one input for each independent data channel. ld[(n C 1):0]r[7:0] o low-speed demultiplexed data bytes retimed to recovered 77.76 mhz clocks. lckr[(n C 1):0] o low-speed 77.76 mhz recovered clocks. lck78 o low-speed (77.76 mhz) pll divide-down clock. can be used as a pll activity monitor point. this buffered version of internal transmit 77.76 mhz clock can be used to time data transfer into the transmitter. ldat[(n C 1):0]x[7:0] i 77.76 mhz data byte inputs to transmitter. hdout[(n C 1):0] o 622.08 mbits/s serial data outputs. ref78 i 77.76 mhz reference clock input to clock synthesizer. rext i connects to external 10 k w 1% resistor that is tied to ground potential (v ssa ) on the circuit pack. provides reference current to on-chip pll. mreset i (active-high). asynchronous master reset for macrocell initialization. also used in test mode to reset test circuitry. pllpwrdn i (active-high). pll powerdown for i ddq testing. rxpwrdn[(n C 1):0] i (active-high). per-channel powerdown of receiver.
data sheet CDRM622 june 1999 622 mbits/s multichannel digital timing recovery macrocell 5 lucent technologies inc. hardware interface (continued) 5-7714(f)r.2 figure 2. 78 mhz interfaces clock synthesizer phase error detector output data relative to output clock 1.0 ns 16 phase 622 receiver ck/8 byte 78 mhz stdcells (test logic) d s s q invert clock to use positive edge flip-flop q s s d ck/8 78 mhz ref78 lck78 byte transmitter 622 mhz input data setup/hold 1.9 ns/0.2 ns 78 mhz CDRM622 pll reference clock
CDRM622 data sheet 622 mbits/s multichannel digital timing recovery macrocell june 1999 6 lucent technologies inc. simulation interface pll bypass device simulating, debugging, and testing with a working pll is not recommended. therefore, a test mode that bypasses the pll is provided. functional simulation and factory testing can make use of this mode. the logic of the data paths remain functional. only the 622.08 mhz clock source is changed to the test clock. for factory test- ing, the pll is separately exercised and monitored through the test port. figure 3 illustrates this mode. logical timing figure 4 and figure 5 illustrate the functional timing relationships during pll bypass mode operation. internal clock synchronization when the pll is bypassed, the internal clock dividers are not automatically aligned with the phase of the input ref- erence clock. resets are provided as an aid to force a relationship. during pll bypass, the clock dividers are clocked by the test clock. the first falling edge of the test clock after the resets become inactive will generate a ris- ing edge of the internal 77.76 mhz clocks. pll bypass simulation test benches should be designed so that the device input signals driving tstclk, ref78, resetrn , and resettn are sequenced to closely align the inter- nal clocks with the reference clock. figure 6 illustrates this sequence. table 2. simulation si g nals signal name type description bypass i (active-high). enables functional bypassing of the 622 mhz clock synthesis with tstclk. receiver and transmitter pass data in a logically correct manner based on the test clock timing. tstclk i test clock for emulation of 622.08 mhz clock during pll bypass. this input can run up to 155 mhz for factory testing. also used for low-speed fault coverage testing. resettn i (active-low). resets transmitter clock division counter to enable synchronizing the internal 77.76 mhz clock to the reference clock during pll bypass. resetrn i (active-low). resets receiver clock division counter to enable synchronizing the recovered 77.76 mhz clocks to the reference clock during pll bypass.
data sheet CDRM622 june 1999 622 mbits/s multichannel digital timing recovery macrocell 7 lucent technologies inc. simulation interface (continued) 5-5834(f).dr.1 figure 3. pll bypass mode block diagram select loopbkch[(n C 1):0] hdin[(n C 1):0] tstclk lck78 ldat[(n C 1):0]x[7:0] lckr[(n C 1):0] ld[(n C 1):0]r[7:0] bsipad[(n C 1):0] bscanen hdout[(n C 1):0] cdr (tstclk divide by 8) clock/data alignment retime parallel to serial (78 mbytes/s to 622 mbits/s) mux loopbken bypass (= 1) serial to parallel (622 mbits/s to 78 mbytes/s) demux boundary scan resetrn resettn bsopad[(n C 1):0]
CDRM622 data sheet 622 mbits/s multichannel digital timing recovery macrocell june 1999 8 lucent technologies inc. simulation interface (continued) 5-5836 (f).d figure 4. 622.08 mbits/s receive (pll bypass mode) timing 5-5837 (f).b figure 5. 622.08 mbits/s transmit (pll bypass mode) timing lsb msb msb lsb msb lsb msb lsb tstclk hdin[(n C 1):0] lckr[(n C 1):0] ld[(n C 1):0]r[7:0] 012345678910111213 00 8a 59 e4 012345678910111213 lck78 ldat[(n C 1)x[7:0] tstclk hdout[(n C 1):0] e5 c9 8a bf fast slow gate delays msb lsb
data sheet CDRM622 june 1999 622 mbits/s multichannel digital timing recovery macrocell 9 lucent technologies inc. simulation interface (continued) 5-5838 (f).er.1 notes: during pll bypass mode, tstclk is asynchronous to the ref78 input of the CDRM622; therefore, test resets (resettn and resetrn ) were added to allow establishing a relationship between the internally generated 77.76 mhz clocks and the reference clocks. resetrn allows synchronization of the 77.76 mhz recovered clocks in the receiver. resettn allows synchronization of the 77.76 mhz clock internal to the transmitter. tstclk should be stopped high while the resets change but needs to toggle at least four clock cycles while resets are active. figure 6. synchronization of CDRM622 generated clocks during bypass mode test interface boundary scan in order to avoid loading the high-speed data signals unnecessarily, access has been provided through the macro- cell. the state of the input pads can be monitored at buffered test outputs. the state of the output pads can be con- trolled through a multiplexer built into the macrocell data path. table 3. s y stem test si g nals signal name type description bsipad[(n C 1):0] o provides buffered monitor points reflecting state of the 622.08 mbits/s device input pads for use in boundary scan. bsopad[(n C 1):0] i provides access to 622.08 mbits/s output pads for boundary scan. output boundary-scan multiplexers are built into the macrocell. bscanen i (active-high). enables boundary-scan values to control 622.08 mhz output device pins. loopbken i (active-high). enables 622.08 mbits/s loopback mode. all transmit outputs are directed into the receivers. overrides individual channel loopback controls. loopbkch[(n C 1):0] i (active-high). enables 622.08 mbits/s loopback mode on a per-channel basis. 8a 96 e4 ld[(n C 1):0]x[7:0] hdout[(n C 1):0] tstclk ref78 resettn lckr[(n C 1):0] tstclk stopped for a minimum of ten clock cycles lck78 resetrn
CDRM622 data sheet 622 mbits/s multichannel digital timing recovery macrocell june 1999 10 lucent technologies inc. test interface (continued) high-speed loopback the output of the transmitter can be looped back into the receiver. this feature enables factory testing 622 mbits/s circuitry on a test set only capable of 200 mhz clocking. system product diagnostics may also find a use for this mode. the loopback function can be selected on a per-channel basis or by a global override. cdr testing built-in test cirtuitry is included as part of the macrocell in order to ensure quality of manufacture. test access and control has been added to facilitate characterization and evaluation of the macrocell function. macrocell testing is added by lucent to verify pll, high-speed data paths, and fault coverage within the macrocell. one such test configures the macrocell in high-speed loopback with transmit pattern generation and receive byte alignment in order to observe 77.76 mbytes/s data after passing through both transmitter and receiver at 622.08 mbits/s. this test requires only the pll reference clock to be sourced from the factory test set. also, each of the recovered channels (clock and data byte) can be brought out through the test port one channel at a time, and the synthesized clock, divided by eight, is brought out for frequency measurement and evaluation. macrocell testing is set up by an internal control register that is written through a 3-pin serial test interface. built-in testing cannot verify the 78 mhz interface connections to the device logic. therefore, at least one test exer- cising the functional data path through the macrocell using pll bypass is required from the device logic designers. test access in order to accomplish these tests, access is required to approximately 20 test signals through the device pins. test pins can be multiplexed with other pins and tstmode = 1 can be used as an indication when cdr test access is needed. in addition, to standard manufacture testing, access to built-in test features has been useful during func- tional board-level prototype prove-in. cdr testing requires access to the following signals from the device pins : tstmode, bypass, tstclk, resetrn , resettn , tstshftld, ecsel, exdnup, etoggle, loopbken, tstphase, tstmux[8:0]. ref78, mreset, and hdin[(n C 1):0] are also used during testing but are expected to be controllable through functional device pins. ref78 should be controllable through the reference clock input to the device. a 155 mhz reference clock pin which is divided on-chip to 78 mhz is acceptable. mreset should be controllable through the device powerup reset pin. table 4. cdr test si g nals signal name type description tstmode i (active-high). enables cdr test mode. tstshftld i (active-high). enables the test mode control register for shifting in selected tests by a serial port (exdnup). serial stream setup is 18 bits long. ecsel i (active-high). enables external manual test control of 622.08 mhz clock phase selection through etoggle and exdnup inputs. etoggle i (active +pulse). moves 622.08 mhz clock selection one phase per positive pulse >50 ns. exdnup i direction of phase change: 0 = down; 1 = up. tstphase i (active-high). controls bypass of 16 pll-generated phases with 16 low- speed phases, generated by test logic. tstmux[8:0] o test mode output port. can monitor recovered channel 77.76 mbytes/s data byte and clock. selection under control of test mode register.
data sheet CDRM622 june 1999 622 mbits/s multichannel digital timing recovery macrocell 11 lucent technologies inc. electrical and timing characteristics table 5. absolute maximum ratin g s 1. at 3.3 v, power is estimated by 300 mw + 50 mw per rx channel + 10 mw per tx channel. table 6. recommended o p eratin g conditions table 7. receiver s p ecifications 1. 622 mbits/s scrambled data stream conforming to sonet sts-12 and sdh stm-4 data format using either a pn7 or pn9 sequence. n pn7 charateristic is 1 + x 6 + x 7 . n pn9 charateristic is 1 + x 4 + x 9 . 2. this sequence should not occur more than once per minute. 3. translates to a frequency change of 500 ppm. 4. a unit interval for 622 mbits/s data is 1.6075 ns. table 8. transmitter s p ecifications table 9. s y nthesizer s p ecifications 1. external 10 k w resistor to analog ground required. 2. translates to a frequency change of 500 ppm. parameter conditions min t yp max unit power dissipation 16 channels at 3.3 v 1.25 1 w parameter conditions min t yp max unit supply voltage 3.135 3.465 v parameter conditions min t yp max unit input data 1 stream of nontransitional 622 mbits/s 2 60 bits phase change, input signal over a 200 ns time interval 3 100 ps eye opening 4 0.4 uip-p jitter tolerance jitter tolerance: 250 khz 25 khz 2 khz 0.6 6 60 uip-p uip-p uip-p parameter conditions min t yp max unit output jitter, generated 250 khz to 5 mhz (measured with a spectrum analyzer) 0.2 uip-p parameter conditions min t yp max unit pll 1 loop bandwidth 6mhz jitter peaking 2db powerup reset time 10 s lock aquisition time 1ms input reference clock frequency 77.76 mhz frequency deviation 20 ppm phase change over a 200 ns time interval 2 100 ps
CDRM622 data sheet 622 mbits/s multichannel digital timing recovery macrocell june 1999 12 lucent technologies inc. silicon layout considerations 5-7715(f)r.1 figure 7. power supply connections integrity of signal transfer from the i/o buffer figure 8 shows a repeater configuration recomended to ensure the integrity of the signal transfer from the i/o buffer to the macrocell. 5-7716(f) notes: use standard-cell sbix16s as repeater buffers for 622 mbits/s data (in pairs). power supplies should be tied to the high-speed i/o buffer and the digital macrocell source. routing: 1 m wide and 4 m spacin g . remain in one metal level as much as is reasonable. use double contact windows when changing levels. repeaters can drive up to 2000 m. evenly distribute load on repeaters (approximately). transmitter can drive up to 2000 m. lvds receivers can drive up to 2000 m. figure 8. 622 mbits/s repeater recomendations device supplies device supplies device supplies v dd v dda v ssa v ss cdr macrocell analog supplies: isolated to the circuit board <3 w macrocell digital supplies: tied to high-speed i/o buffer supplies isolated from device supplies <0.5 w lvds lvds
data sheet CDRM622 june 1999 622 mbits/s multichannel digital timing recovery macrocell 13 lucent technologies inc. notes
d a t a s h e et CDRM622 622 mbits/s multi c hannel digital timing rec o ve r y mac r ocell j une 1999 l u cent t e chnolo g ies inc . res e rves t he r i g ht t o mak e cha n ges t o th e pro d uct(s ) o r info r matio n cont a ined h erei n withou t notice . n o liabilit y i s assu m ed as a r esult o f thei r use or a pplicatio n . no r ights u n der a ny pa t ent acc o mpa n y the s a le of a ny such p rod u ct(s ) or in f orm a tion. co p yrigh t ? 199 9 luce n t t echn o logies i n c. all rights res e rved june 1999 ds99 - 153ntbb f o r a d d i ti o n a l i n format i o n , co n tact y our mi c roelectroni c s group a ccoun t m an a g e r o r t h e f o l l o wi n g : i n terne t : ht t p : / /ww w .l u ce n t . com / mi c ro e-m a il: docm a st e r@ m ic r o.lu c ent. c om n. a m eri c a : m icr o e l e ctro n i c s gro u p, l uc e nt t e c h n o lo g i e s in c ., 5 5 5 u n i o n b o u l e v a r d , r o o m 3 0l - 1 5 p - b a , a l l e n t ow n , p a 1 8 1 03 1 - 8 0 0 - 3 7 2 - 2 44 7 , f a x 6 1 0 - 7 1 2- 4 1 06 ( in c a n a d a : 1 -8 00 -5 5 3 - 2 4 4 8 , f ax 610-712-4106 ) asia p a c if i c : m icr o e l e ctro n i c s gro u p, l uc e nt t e c h n o l o g i e s s i n g apore p te. ltd . , 77 s c ience park drive , #03-18 cin t ech i ii , s in g ap o r e 1 1 8 2 56 t e l . ( 6 5) 7 78 8 8 33 , f ax ( 6 5 ) 7 7 7 7 4 9 5 c hi n a: m i c r oe l e c t r o n i c s g r ou p , lu c e nt t e c hn o l o g i e s ( c h i n a ) c o . , lt d . , a -f 2 , 2 3/ f , za o f o n g u n i ver s e b u il d in g , 1 8 0 0 z h on g s h a n x i ro a d, s ha n g h a i 20 0 2 3 3 p . r . c h i n a t e l . (8 6 ) 21 6 4 40 0 46 8 , e x t. 3 1 6 , f ax ( 8 6 ) 2 1 6 4 4 0 0 6 52 ja p a n : m icr oe l e ctro n i c s gro u p, l uc e nt t e c h n o lo g i e s j a p a n l td . , 7 - 1 8 , hi g a s h i - go t an d a 2 -c ho m e , s h i n a g awa-ku, t ok y o 1 41 , j ap a n t e l. ( 8 1 ) 3 54 2 1 1 6 0 0 , f ax ( 8 1 ) 3 5 4 2 1 1 7 00 e u r op e : da t a r e q uests: microelectronics group d a t a line : t e l . ( 4 4 ) 70 0 0 582 368 , f a x ( 4 4 ) 1 1 89 3 2 8 1 48 t e c h n i c a l in q u i ri e s: ge r ma n y : ( 4 9 ) 89 9 5 0 8 6 0 (m u n i ch ) , united kingdom: ( 4 4 ) 1 3 4 4 8 6 5 9 0 0 ( a sc o t ) , f r a n ce : ( 3 3) 1 40 83 68 0 0 ( p a r i s ) , sweden : ( 46 ) 8 5 9 4 6 07 0 0 ( sto c khol m ) , f in l a n d: ( 3 58 ) 9 4 3 5 4 2 8 00 ( h e ls i n k i ) , i t a l y : ( 3 9 ) 0 2 6 6 0 8 13 1 ( m i l a n ) , s p a i n : ( 3 4 ) 1 8 0 7 1 4 4 1 (m a dr i d)

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